1. Field of the Invention
The disclosed technology relates in general to integrated circuit (IC) design and testing, and in particular to a test architecture for 3D stacked ICs (SIC) interconnected by through-substrate vias (TSVs) and a method thereto.
2. Description of the Related Technology
The semiconductor industry is preparing itself for 3D-SICs based on TSVs. TSVs are conducting nails which extend out of the back-side of a thinned-down die and enable the vertical interconnect to another die. TSVs are high-density, low-capacity interconnects compared to traditional wire-bonds, and hence allow for many more interconnections between stacked dies, while operating at higher speeds and consuming less power. TSV-based 3D technologies enable the creation of a new generation of ‘super chips’ by opening up new architectural opportunities. Combined with their smaller form factor and lower overall manufacturing cost, 3D-SICs have many compelling benefits, and hence their technology is quickly gaining ground. Like all micro-electronics, TSV-based die stacks have a manufacturing process that is sensitive to defects, and hence 3D-SICs need to undergo electrical testing to ensure product quality. While the process and design technology is getting to maturity, testing 3D-SICs for manufacturing defects is considered by many as a major, still largely unresolved obstacle to make these devices a product reality.
Currently, different types of test architectures exist.
A commonly-used test access architecture for PCBs is based on IEEE Std. 1149.1, Boundary Scan (a.k.a. ‘JTAG’). In order for chips to be compliant to IEEE 1149.1, a small hardware wrapper is added to them. IEEE 1149.1 works through a narrow single-bit interface, as every JTAG terminal requires an additional chip pin and these are considered expensive. Fortunately, the prime focus of IEEE 1149.1 is PCB interconnect testing, and that requires only a small number of test patterns.
The single-bit interface pins are called TDI and TDO, and they are adapted for transporting both instructions and test data. The control interface consists of the pins TCK, TMS (and optionally TRSTN). For an example PCB 10 containing three chips, Chip A, Chip B and Chip C, a common JTAG-based test access architecture 11 is depicted in FIG. 1. The control signals TCK (clock), TMS (Mode Select) and optionally TRSTN are broadcast to all chips Chip A, Chip B, Chip C, while the TDI-TDO pins are concatenated through the chips. The broadcast control signals can configure a TAP Controller finite state machine 12 in a mode in which it is willing to receive instructions, which are subsequently scanned into the Instruction Register (IR) 13 via the daisy-chained TDI-TDO interface. It is to be noted that this allows for different instructions for different chips; for example, Chip B can be configured in INTEST mode (internal test of the chip), while Chips A and C are configured in BYPASS mode. Then, the chips are brought into their instructed test modes via the broadcast control signals and test data is scanned in and out again via the daisy-chained TDI-TDO interface. The selected test data register (e.g., the bypass register 14, a boundary scan register (BSR) 15, or a chip-internal scan chain 16) depends on the instruction, and can be different for different chips; in any case, it is a single shift register, as shown in FIG. 1.
A commonly-used test access architecture for (two-dimensional) SOCs containing embedded IP cores is based on IEEE Std. 1500. Like IEEE 1149.1, IEEE 1500 adds a small hardware wrapper around the module-under-test. As shown in FIG. 2, the test access architecture for an IEEE 1500-based SOC shows similarities to IEEE 1149.1-based PCBs. For an example SOC 20 containing three cores, Core A, Core B and Core C, a common IEEE 1500-based test access architecture 21 is depicted in FIG. 2.
Control signals TCK, TMS and optionally TRSTN are broadcast to all cores Core A, Core B, Core C. Once configured in the appropriate mode via the IEEE 1149.1 test structures, instructions are shifted into the wrapper instruction register (WIR) 23 of the cores via the daisychained WSI-WSO interface. That same instruction interface also doubles as single-bit test data interface. However, next to the similarities, there are also significant differences between IEEE 1149.1- and IEEE 1500-based test access architectures. Below, the most important ones are listed.                Unlike IEEE 1149.1, the focus of IEEE 1500 is not (only) on testing wiring interconnects between cores. First of all, the interconnect circuitry in between IP cores typically does not consist only of wires, but is often formed by deep sequential logic. In addition, IEEE 1500 is meant to support also the testing of the cores themselves, and IP cores are often significantly-sized and complex design entities. Therefore, the test data volumes involved are typically quite large, and a single-bit test data interface would not suffice. Hence, IEEE 1500 has an optional n-bit (‘parallel’) test data interface (named WPI and WPO), where n can be scaled by the user to match the test data volume needs of the IP core in question.        Adding wider interfaces to embedded IP cores does not add chip pins as in IEEE 1149.1, but only core terminals, which are considered to be significantly less expensive than chip pins.        IEEE 1149.1 has two (or three) standardized control pins TCK, TMS, TRSTN, which are expanded within the chip by the TAP Controller 12. IEEE 1500 has no TAP Controller, but receives it control signals directly. These are six (or seven) signals: WRCK, WRSTN, SELECTWIR, SHIFTWR, CAPTUREWR, UPDATEWR (and optionally TRANSFERDR).        
FIG. 2 also features a parallel wrapper bypass 24. This bypass 24 is not mandated by IEEE 1500, but often implemented to shorten the test access path to other cores in the same test access mechanism (TAM). It is the task of the switch boxes 25, 26 in FIG. 2 to make an effective mapping between the active WIR instruction mode and the TAM-to-chain connections.
IEEE 1500 only standardizes the core-level test wrapper, and not the SOC-level test access architecture of the optional parallel TAMs. At the SOC-level, optimizations can be made w.r.t. TAM type, TAM architecture, and corresponding test schedule. In a typical implementation, as shown in FIG. 2, the SOC 20 itself may be equipped with an IEEE 1149.1 wrapper to facilitate board-level testing. The IEEE 1500 serial interface (WSC, WSI, and WSO) may be multiplexed onto the IEEE 1149.1 Test Access Port to save otherwise additional test pins. The IEEE 1500 parallel interface (WPI and WPO) can be multiplexed onto the functional external pins, as is common for regular scan chains; this also saves otherwise additional test pins.
“Dean L. Lewis and Hsien-Hsin S. Lee, ‘A Scan-Island Based Design Enabling Prebond Testability in Die-Stacked Microprocessors’ Proc. IEEE International Test Conference (ITC), October 2007” is dedicated to testability of 3D-SICs. It focuses on pre-bond die testing, required to achieve acceptable compound stack yields. Testing incomplete products as formed by the various stack tiers is identified as a potential problem. In the paper a ‘scan island’ approach is proposed, which is essentially the wrapper technology from IEEE 1149.1 and IEEE 1500.
Most other work on 3D-SIC testing implicitly proposes a test access architecture, while focusing on optimizing the design parameters of that architecture to minimize the resulting test length and/or the associated wire length. “Xiaoxia Wu, Paul Falkenstern, and Yuan Xie, ‘Scan Chain Design for Three-dimensional Integrated Circuits (3D ICs)’, Proc. International Conference on Computer Design (ICCD), p. 208-214, October 2007” describe three scan chain optimization approaches for 3D-SICs. Implicitly, this paper assumes that a single logic test unit is partitioned over multiple tiers. In “Xiaoxia Wu et al., Test-Access Mechanism Optimization for Core-Based Three-Dimensional SOCs', Proc. International Conference on Computer Design (ICCD), p. 212-218, October 2008”, the authors propose a core-based design and test approach (as common for 2D-SOCs) in which each core resides on a single tier. The paper proposes an ILP-based (integer linear programming) Test Access Mechanism (TAM) optimization approach, which tries to minimize the resulting test length under a constraint for the number of additional ‘test TSVs’. Both papers focus exclusively on post-bond stack testing, and ignore the requirements for pre-bond die testing.
Jiang et al. describe in “Li Jiang, Lin Huang, and Qiang Xu, ‘Test Architecture Design and Optimization for Three-Dimensional SoCs’, Proc. Design, Automation, and Test in Europe (DATE), pages 220-225, April 2009”, a TAM optimization approach based on simulated annealing that minimizes test length and TAM wire length with a user-defined cost weight factor. They assume a modular core-based 3DSIC test approach and take both pre-bond and post-bond test lengths into account. The paper lacks constraints on wafer and packaged stack test access, due to which it unrealistically allows TAMs to start and end at any stack tier. Successor paper, “Li Jiang et al., ‘Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint’, Proc. International Conference on Computer-Aided Design (ICCAD), p. 191-196, November 2009”, remedies this partly, by working with pre-bond tests that are applied through dedicated probe pads at the die in question, for which a maximum count is assumed. The paper proposes heuristics that determine a post-bond stack test architecture, from which segments are reused as much as possible to build additional die-level test architectures for the pre-bond tests, while meeting the maximum probe pad count constraint and minimizing test length and TAM wire length. Adding dedicated probe pads is expensive in terms of substrate area, and hence is to be avoided.
Chih-Yen Lo et al. describe in “Chih-Yen Lo, Yu-Tsao Hsing, Li-Ming Denq and Cheng-Wen Wu, ‘SOC Test Architecture and Method for 3D-IC’, DATE '09 Friday Workshop on 3D integration, Nice, Apr. 24, 2009” that, to consider the yield issues of 3D-IC manufacturing, they perform a known-good-die (KGD) test before die stacking. Every time a new KGD is mounted on the original stacked chip, a through-substrate via test is performed for 3D interconnect verification between the two top-most layers. A test architecture is described which consists of an extended JTAG/IEEE 1149.1 Test Access Port Controller and multiplexer-based test access mechanism (TAM) buses.
There is room for improved test architectures of 3D stacked ICs.